Apollo PRISM - Compilers

Compilers

The compilers used with the systems were expected to dedicate more time during compilation to making effective use of the registers and cleaning the instruction stream. By doing instruction scheduling in the compiler, this design avoided the problems and complexity of dynamic instruction scheduling (where instructions for multiple functional units must be selected carefully in order to avoid interdependencies between intermediate values) encountered in superscalar designs such as Digital Equipment Corporation's Alpha.

In some respects, the VLIW design can be thought of as "super-RISCy", as it offloads the instruction selection process to the compiler as well. In the VLIW design, the compiler examines the code and selects instructions that are known to be "safe", and then packages them into longer instruction words. For instance, for a CPU with two functional units, like the PRISM, the compiler would find pairs of safe instructions and stuff them into a single larger word. Inside the CPU, the instructions are simply split apart again, and fed into the selected units.

This design minimizes logical changes to the CPU as functional units are added, as the compiler is handling the instruction selection. However, this also ties the compiled code very tightly to the processor design; for instance, if a new generation of the CPU adds additional functional units, all programs running on it must be re-compiled so the compiler can re-arrange the instructions again, perhaps four-wide instead of two-wide. In comparison, a more traditional design like the PowerPC (PPC) has seen dramatic internal changes, yet code written for the first PPC's will still run without modification on the latest versions. The cost for this is an increasing amount of chip space that has to be dedicated to instruction scheduling.

The Apollo compilers were the first commercial compilers to use data-flow analysis and single static assignment techniques.