45 Nanometer - Example: Intel's 45 Nm Process

Example: Intel's 45 Nm Process

At IEDM 2007, more technical details of Intel's 45 nm process were revealed.

Since immersion lithography is not used here, the lithographic patterning is more difficult. Hence many lines have been lengthened rather than shortened. A more time-consuming double patterning method is used explicitly for this 45 nm process, resulting in potentially higher risk of product delays than before. Also, the use of high-k dielectrics is introduced for the first time, to address gate leakage issues. For the 32 nm node, immersion lithography will begin to be used by Intel.

• 160 nm gate pitch (73% of 65 nm generation)
• 200 nm isolation pitch (91% of 65 nm generation) indicating a slowing of scaling of isolation distance between transistors
• Extensive use of dummy copper metal and dummy gates
• 35 nm gate length (same as 65 nm generation)
• 1 nm equivalent oxide thickness, with 0.7 nm transition layer
• Gate-last process using dummy polysilicon and damascene metal gate
• Squaring of gate ends using a second photoresist coating
• 9 layers of carbon-doped oxide and Cu interconnect, the last being a thick "redistribution" layer
• Contacts shaped more like rectangles than circles for local interconnection
• Lead-free packaging
• 1.36 mA/um nFET drive current
• 1.07 mA/um pFET drive current, 51% faster than 65 nm generation, with higher hole mobility due to increase from 23% to 30% Ge in embedded SiGe stressors

In a recent Chipworks reverse-engineering, it was disclosed that the trench contacts were formed as a "Metal-0" layer in tungsten serving as a local interconnect. Most trench contacts were short lines oriented parallel to the gates covering diffusion, while gate contacts where even shorter lines oriented perpendicular to the gates.

It was recently revealed that both the Nehalem and Atom microprocessors used SRAM cells containing eight transistors instead of the conventional six, in order to better accommodate voltage scaling. This resulted in an area penalty of over 30%.